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16-bit, 1.5 lsb inl, 250 ksps pulsar differential adc in msop data sheet ad7687 rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2005C2015 analog devices, inc. all rights reserved. technical support www.analog.com features 16-bit resolution with no missing codes throughput: 250 ksps inl: 0.4 lsb typ, 1.5 lsb max (23 ppm of fsr) dynamic range: 96.5 db snr: 95.5 db at 20 khz thd: ?118 db at 20 khz true differential analog input range v ref 0 v to v ref with v ref up to vdd on both inputs no pipeline delay single-supply 2.3 v to 5.5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface proprietary serial interface: spi/qspi?/microwire/dsp compatible daisy-chain multiple adcs and busy indicator power dissipation 1.35 mw at 2.5 v/100 ksps, 4 mw at 5 v/100 ksps, and 1.4 w at 2.5 v/100 sps standby current: 1 na 10-lead msop and 10-lead, 3 mm 3 mm lfcsp pin-for-pin compatible with ad7685 , ad7686 , and ad7688 applications battery-powered equipment data acquisitions instrumentation medical instruments process controls typical application circuit ad7687 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v to vdd 3- or 4-wire interface (spi, daisy chain, cs) 0.5v to 5v 2.5 to 5v vref 0 02972-002 vref 0 figure 1. general description the ad7687 1 is a 16-bit, charge redistribution, successive approximation, analog-to-digital converter (adc) that operates from a single power supply, vdd, between 2.3 v to 5.5 v. it contains a low power, high speed, 16-bit sampling adc with no missing codes, an internal conversion clock, and a versatile serial interface port. the device also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. on the cnv rising edge, the ad7687 the samples the voltage difference between in+ and in? pins, which can range from ?v ref to +v ref . the reference voltage, v ref , is applied externally and can be set up to the supply voltage. the power consumption of the device scales linearly with throughput. the spi-compatible serial interface also features the ability to daisy-chain several adcs on a single 3-wire bus and provides an optional busy indicator by means of the sdi pin. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic using the separate supply vio. the ad7687 comes in a 10-lead msop or a 10-lead lfcsp with operation specified from ?40c to +85c. table 1. msop, lfcsp/sot-23 16-bit pulsar ? adc type 100 ksps 250 ksps 500 ksps true differential ad7684 ad7687 ad7688 pseudo ad7683 ad7685 ad7686 differential/unipolar ad7694 unipolar ad7680 1 protected by u.s. patent 6,703,961.
ad7687* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7687 evaluation kit ? precision adc pmod compatible boards documentation application notes ? an-931: understanding pulsar adc support circuitry ? an-932: power supply sequencing data sheet ? ad7687: 16-bit, 1.5 lsb inl, 250 ksps pulsar differential adc in msop data sheet product highlight ? [no title found] product highlight ? 8- to 18-bit sar adcs ... from the leader in high performance analog ? lowest-power 16-bit adc optimizes portable designs (eeproductcenter, 10/4/2006) user guides ? ug-340: evaluation board for the 10-lead family 14-/16-/ 18-bit pulsar adcs ? ug-682: 6-lead sot-23 adc driver for the 8-/10-lead family of 14-/16-/18-bit pulsar adc evaluation boards software and systems requirements ? ad7687 fmc-sdp interposer & evaluation board / xilinx kc705 reference design ? bemicro fpga project for ad7687 with nios driver tools and simulations ? ad7685 ibis models reference designs ? cn0225 reference materials technical articles ? ms-1779: nine often overlooked adc specifications ? ms-2210: designing power supplies for high speed adc tutorials ? mt-074: differential drivers for precision adcs design resources ? ad7687 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7687 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7687 data sheet rev. e | page 2 of 26 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical applicat ion circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 timing specifications .................................................................. 6 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 terminology .................................................................................... 10 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 14 circuit information .................................................................... 14 converter operation .................................................................. 14 typical connection diagram ................................................... 15 analog input ............................................................................... 16 driver amplifier choice ........................................................... 17 single - to - differential driver .................................................... 17 voltage reference input ............................................................ 17 powe r supply ............................................................................... 17 supplying the adc from the reference .................................. 18 digital interface .......................................................................... 18 cs mode, 3 - wire without busy indicator ........................... 19 cs mode, 3 - wire with busy indicator .................................. 20 cs mode, 4 - wire without busy indicator ........................... 21 cs mode, 4 - wire with busy indicator .................................. 22 chain mode without busy indicator .................................... 23 chain mode with busy indicator ........................................... 24 applications information .............................................................. 25 layout .......................................................................................... 25 evaluating the performance of the ad7687 ............................... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26
data sheet ad7687 rev. e | page 3 of 26 revision history 12/15rev. d to rev. e deleted figure 1; renumbered sequentially ................................. 1 changes to features section and general description section ....... 1 change to signal-to-(noise + distortion) parameter, table 2 ......... 4 added timing diagrams section .................................................... 7 moved figure 2 and figure 3 ........................................................... 7 changes to table 8 ............................................................................ 9 changes to figure 7 caption, figure 8 caption, figure 10 caption, and figure 11 caption .................................................... 11 added theory of operation section ............................................ 14 changes to analog input section ................................................. 16 changes to drive amplifier choice section, table 10, figure 30, voltage reference input section, and power supply section ......... 17 changes to supplying the adc from the reference section and digital interface section ......................................................... 18 changed cs mode, 3-wire, no busy indicator section to cs mode, 3-wire without busy indicator section ........................ 19 changes to cs mode, 3-wire without busy indicator section ... 19 changes to cs mode, 3-wire with busy indicator section ...... 20 changed cs mode, 4-wire, no busy indicator section to cs mode, 4-wire without busy indicator section ........................ 21 changes to cs mode, 4-wire without busy indicator section ... 21 changes to cs mode, 4-wire with busy indicator section .......... 22 changed chain mode, no busy indicator section to chain mode without busy indicator section ....................................... 23 changes to chain mode without busy indicator section, figure 42 caption, and figure 43 caption ................................... 23 changes to chain mode with busy indicator section ............. 24 changes to layout section ............................................................. 25 changed application hints section to application recommendations section ............................................................ 25 changes to ordering guide ........................................................... 26 4/15rev. c to rev. d added patent note, note 1 .............................................................. 1 changes to snr degradation equation, driver amplifier choice section ................................................................................. 16 changes to ordering guide ........................................................... 26 7/14rev. b to rev. c deleted qfn ................................................................... throughout changed application diagram section to typical application circuit section ................................................................................... 1 change to features section .............................................................. 1 added note 1 ..................................................................................... 1 changes to figure 27 ...................................................................... 14 changes to evaluating the performance of the ad7687 section .............................................................................................. 24 updated outline dimensions ........................................................ 25 changes to ordering guide ........................................................... 26 8/11rev. a to rev. b changes to table 7 ............................................................................ 7 changes to ordering guide ........................................................... 26 2/11rev. 0 to rev. a deleted qfn in development note ............................ throughout changes to table 6 ............................................................................ 7 added thermal resistance section and table 7 ........................... 7 changes to figure 6 and table 8 ..................................................... 8 updated outline dimensions ........................................................ 25 changes to ordering guide ........................................................... 26 4/05revision 0: initial version
ad7687 data sheet rev. e | page 4 of 26 specifications vdd = 2.3 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = ? 40c to +85c, unless otherwise noted. table 2. parameter test conditions /comments min typ max unit resolution 16 bits analog input voltage range in + ? in? ?v ref +v ref v absolute input voltage in + and i n? ?0.1 v ref + 0.1 v common - mode input range in+ and in? 0 v ref /2 v ref /2 + 0.1 v analog input cmrr f in = 250 khz 65 db leakage current at 25c acquisition phase 1 na input impedance see the analog input section accuracy no missing codes 16 bits differential linearity error ?1 0.4 +1 lsb 1 integral linearity error ?1.5 0.4 +1.5 lsb transition noise ref = vdd = 5 v 0.35 lsb gain error 2 , t min to t max 2 6 lsb gain error temperature drift 0.3 ppm/c offset error 2 , t min to t max vdd = 4.5 v to 5.5 v 0.1 1.6 mv vdd = 2.3 v to 4.5 v 0.7 3.5 mv offset temperature drift 0.3 ppm/c power supply sensitivity vdd = 5 v 5% 0.05 lsb throughput conversion rate vdd = 4.5 v to 5.5 v 0 250 ksps vdd = 2.3 v to 4.5 v 0 200 ksps transient response full - scale step 1.8 s ac accuracy dynamic range v ref = 5 v 95.8 96.5 db 3 signal -to - noise ratio f in = 20 khz, v ref = 5 v 94 95.5 db f in = 20 khz, v ref = 2.5 v 92 92.5 db spurious - free dynamic range f in = 20 khz ?118 db total harmonic distortion f in = 20 khz ?118 db signal -to - (noise + distortion) ratio f in = 20 khz, v ref = 5 v 94 95 db f in = 20 khz, v ref = 5 v, ?60 db input 36.5 db f in = 20 khz, v ref = 2.5 v 92 92.5 db intermodulation distortion 4 115 db 1 lsb means least significant bit. with the 5 v input range, one lsb is 152.6 v. 2 see the terminology section. these s pecifications do include full temperature range variation but do not include the error contribution from the external referen ce. 3 all specifications in db are referred to a fu ll- scale input fs r . tested with an input signal at 0.5 db below full - scale, unless otherwise specified. 4 f in1 = 21.4 khz, f in2 = 18.9 khz, each tone at ?7 db below full - scale .
data sheet ad7687 rev. e | page 5 of 26 vdd = 2.3 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = ? 40c to +85c, unless otherwise noted. table 3. parameter test conditions /comments min typ max unit reference voltage range 0.5 vdd + 0.3 v load current 250 ksps, ref = 5 v 50 a sampling dynamics ? 3 db input bandwidth 2 mhz aperture delay vdd = 5 v 2.5 ns digital inputs logic levels v il ?0.3 + 0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 16 - bits twos complement pipeline delay conversion results available immediately after completed conversion v ol i sink = 500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 2.3 5.5 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 1 , 2 vdd and vio = 5 v, 25c 1 50 na power dissipation vdd = 2.5 v, 100 sps throughput 1.4 w vdd = 2.5 v, 100 ksps throughput 1.35 mw vdd = 2.5 v, 200 ksps throughput 2.7 mw vdd = 5 v, 100 ksps throughput 4 5.5 mw vdd = 5 v, 250 ksps throughput 12.5 mw temperature range 3 specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact sales for extended temperature range.
ad7687 data sheet rev. e | page 6 of 26 timing specification s ?40c to +85c, vdd = 4.5 v to 5.5 v, vio = 2.3 v to 5.5 v or vdd + 0.3 v, whichever is the lowest, unless otherwise stated. s ee figure 2 and figure 3 for load conditions. table 4. parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 2.2 s acquisition time t acq 1.8 s time between conversions t cyc 4 s cnv pulse width ( cs mode) t cnvh 10 ns sck period t sck cs mode 15 ns chain mode vio above 4.5 v 17 ns vio above 3 v 18 ns vio above 2.7 v 19 ns vio above 2.3 v 20 ns sck time low t sckl 7 ns high t sckh 7 ns sck falling edge t o data remains valid t hsdo 5 t o data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 15 ns valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns valid setup time from sck falling edge (chain mode) t ssdisck 3 ns valid hold time from sck falling edge (chain mode) t hsdisck 4 ns high to sdo high (chain mode with busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns
data sheet ad7687 rev. e | page 7 of 26 ?40c to +85c, vdd = 2.3 v to 4.5 v, vio = 2.3 v to 4.5 v or vdd + 0.3 v, whichever is the lowest, unless otherwise stated. s ee figure 2 and figure 3 for load conditions. table 5. parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.7 3.2 s acquisition time t acq 1.8 s time between conversions t cyc 5 s cnv pulse width ( cs mode ) t cnvh 10 ns sck period t sck cs mode 25 ns chain mode vio above 3 v 29 ns vio above 2.7 v 35 ns vio above 2.3 v 40 ns sck time low t sckl 12 ns high t sckh 12 ns sck falling edge t o data remains valid t hsdo 5 t o data valid delay t dsdo vio above 3 v 24 ns vio above 2.7 v 30 ns vio above 2.3 v 35 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 2.7 v 18 ns vio above 2.3 v 22 ns high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 30 ns valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns valid setup time from sck falling edge (chain mode) t ssdisck 5 ns valid hold time from sck falling edge (chain mode) t hsdisck 4 ns high to sdo high (chain mode with busy indicator) t dsdosdi 36 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns valid hold time from cnv rising edge (chain mode) t hsckcnv 8 ns timing diagrams 500a i ol 500a i oh 1.4v to sdo c l 50pf 02972-003 figure 2 . load circuit for digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 02972-004 1 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. figure 3 . voltage levels for timing
ad7687 data sheet rev. e | page 8 of 26 absolute maximum rat ings table 6. parameter rating analog inputs in+ 1 , in? 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperature range jedec j - std -20 1 see the analog input s ection. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for t he worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 7 . thermal resistance package type ja jc unit 10- lead lfcsp 84 2.96 c /w 10- lead msop 200 44 c /w esd caution
data sheet ad7687 rev. e | page 9 of 26 pin configurations and function descriptions 02972-005 ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad7687 top view (not to scale) figure 4. 10-lead ms op pin configuration 02972-006 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9sdi 8sck 7sdo 6 cnv notes 1. for the lfcsp only, the exposed paddle must be connected to gnd. top view (not to scale) ad7687 figure 5. 10-lead lfcsp pin configuration table 8. pin function descriptions pin no. mnemonic type 1 function 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd, referred to the gnd pin. place a 10 f decoupling capacitor as clos e to the pin as possible. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates a conversion and selects the interface mode: chain or cs (depending on the state of sdi). in cs mode, cnv enables the sdo pin when low. in chain mode, the da ta is read while cnv is high. 7 sdo do serial data output. the conversion resu lt is output on this pin. it is sync hronized to sck. sdo also acts as the busy indicator if the feature is enabled. 8 sck di serial data clock input. th is input primarily shifts da ta out on sdo when data is valid. in chain mode, the state of sck determines if the busy indicator feature is enabled. if sck is low during the cnv rising edge, the busy feature is disabled. if it is high during the cnv rising edge, the busy feature is enabled. 9 sdi di serial data input. this inp ut serves multiple functions. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv risi ng edge. in this mode, sdi is used as a data input to daisy chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cnv risi ng edge. in this mode, either sdi or cnv can enable the serial output signals when low, and if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). epad n/a for the lfcsp only, the exposed paddle must be connected to gnd. 1 ai means analog input, di means digita l input, do means digital output, p me ans power, and n/a means not applicable.
ad7687 data sheet rev. e | page 10 of 26 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line dra wn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. measure the deviation from the middle of each code to the true straight line ( see figure 25). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. the dnl is the maximum deviation from this ideal value. it is often specifie d in terms of resolution for which no missing codes are guaranteed. zero error zero error is the differe nce between the i deal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 00 to 100 01) should occur at a level ? lsb above nominal negative full scale (?4.99 9924 v for the 5 v range). the last transition (from 01110 to 01111) sh ould occur for an analog voltage 1? lsb below the nominal full scale (+4.999771 v for the 5 v range.) the gain error is the deviation of the difference between the actual level of t he last transition and the actual level of the first transition from the difference between the idea l levels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious s ignal. effective number of bits (enob) enob is a measure ment of the resolution with a sine wave input. it is related to sinad by the following formula enob = ( sinad db ? 1.76 ) /6.02 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in db. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs sho rted together. the value for dynamic range is expressed in db. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in db. signal -to - (noise + distortion) ratio ( sinad ) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excludin g dc. the value for sinad is expressed in db. aperture delay aperture delay is t he measure of the acquisition performance . it is the time between the rising edge of the cnv input and when the inpu t signal is held for a conversion. transient response transient response is the time required for the adc to acquire its in put accurately after a full - scale step function is applied.
data sheet ad7687 rev. e | page 11 of 26 typical performance characteristics code inl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 16384 32768 49152 65535 02972-001 positive inl = +0.32lsb negative inl = ?0.41lsb figure 6 . integral nonlinearity vs. code 02972-007 counts 300000 250000 150000 200000 100000 50000 0 code in hex 45 46 47 41 42 43 44 0 0 1049 0 0 258680 1391 vdd = ref = 5v figure 7 . histogram of a dc input at the code center, vdd = ref = 5 v frequency (khz) amplitude (db of full scale) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?160 ?140 ?180 0 20 40 60 80 100 120 02972-008 8192 point fft vdd = ref = 5v f s = 250ksps f in = 2.1khz snr = 95.5db thd = ? 1 18.3db 2nd harmonic = ?130db 3rd harmonic = ?122.7db figure 8 . fft plot, vdd = ref = 5 v code dnl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 16384 32768 49152 65535 02972-009 positive dnl = +0.27lsb negative dnl = ?0.24lsb figure 9 . differential nonlinearity vs. code 02972-010 counts 250000 150000 200000 100000 50000 0 code in hex 49 4a 4c 44 46 47 48 0 45 0 60 30721 18 4b 0 0 200403 29918 vdd = ref = 2.5v figure 10 . histogram of a dc input at the code center, vdd = ref = 2.5 v frequency (khz) amplitude (db of full scale) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?160 ?140 ?180 0 20 40 60 80 100 120 02972-011 32768 point fft vdd = ref = 2.5v f s = 250ksps f in = 2khz snr = 92.8db thd = ?115.9db 2nd harmonic = ?124db 3rd harmonic = ?119db figure 11 . fft plot, vdd = ref = 2.5 v
ad7687 data sheet rev. e | page 12 of 26 02972-012 reference voltage (v) 5.5 2.3 2.7 3.5 4.3 5.1 3.1 3.9 4.7 snr, sinad (db) 100 95 85 90 70 snr enob enob (bits) 17.0 15.0 16.0 14.0 13.0 sinad figure 12 . snr, sin a d , and enob vs. reference voltage 02972-013 frequency (khz) 200 0 50 100 150 sinad (db) 100 95 85 90 80 75 70 vref = 5 v , ?10db vref = 2.5 v , ?10db vref = 2.5 v , ?1db vref = 5 v , ?1db figure 13 . s i na d v s. frequency 02972-014 temperature ( c ) 125 ? 55 ? 35 ? 15 5 25 45 65 85 105 snr (db) 100 95 90 85 80 vref = 5v vref = 2.5v figure 14 . snr vs. temperature 02972-015 reference voltage (v) 5.5 2.3 2.7 3.5 4.3 5.1 3.1 3.9 4.7 thd, sfdr (db) ? 100 ? 105 ? 110 ? 115 ? 120 ? 125 ? 130 thd sfdr figure 15 . thd, sfdr vs. reference voltage 02972-016 frequency (khz) 200 0 50 100 150 thd (db) ? 60 ? 70 ? 90 ? 80 ? 100 ? 110 ? 120 vref = 5v, ? 10db vref = 2.5v, ? 10db vref = 5v, ? 1db vref = 2.5v, ? 1db figure 16 . thd vs. frequency 02972-017 temperature (c ) 125 ?55 ?35 ?15 5 25 45 65 85 105 thd (db) ?90 ?100 ?110 ?120 ?130 vref = 5v vref = 2.5v figure 17 . thd vs. temperature
data sheet ad7687 rev. e | page 13 of 26 02972-018 input level (db) 0 ?10 ?8 ?6 ?4 ?2 snr (db) 100 99 98 97 96 95 94 93 92 91 90 vref = 5v vref = 2.5v figure 18 . snr vs. input level supply (v) operating current ( a) 1000 750 500 250 0 2.3 3.1 3.9 4.7 5.5 2.7 3.5 4.3 5.1 02972-019 vio vdd f s = 100ksps figure 19 . operating current vs. supply temperature ( c) power-down current (na) 1000 750 500 250 0 ? 55 ? 35 ? 15 5 25 45 65 85 105 125 02972-020 vdd + vio figure 20 . power - down current vs. temperature temperature ( c) operating current ( a) 1000 750 500 250 0 ? 55 ? 35 ? 15 5 25 45 65 85 105 125 02972-021 vio vdd = 5v vdd = 2.5v f s = 100ksps figure 21 . operating current vs. temperature 02972-022 temperature ( c) 125 ?55 ?35 ?15 5 25 45 65 85 105 offset error and gain error (lsb) 6 4 2 0 ?2 ?4 ?6 gain error offset error figure 22 . offset error and gain error vs. temperatur e 02972-023 sdo capacitive load (pf) 120 0 20 40 60 80 100 t dsdo delay (ns) 25 20 15 10 5 0 vdd = 2.5v, 85c vdd = 3.3v, 25c vdd = 3.3v, 85c vdd = 5v, 85c vdd = 5v, 25c vdd = 2.5v, 25c figure 23 . t dsdo delay vs. capacitance load and supply
ad7687 data sheet rev. e | page 14 of 26 t heory of o peration sw+ msb 16,384c in+ lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 32,768c sw? msb 16,384c lsb 4c 2c c c 32,768c 02972-024 figure 24 . adc simplified schematic circuit information the ad7687 is a fast, low power, single - supply, precise 16 - bit adc using a successive approximation architecture. the ad7687 is capable of converting 250,000 samples per second (250 ksps) and powers down between conversions. when operating at 100 sps, for example, it typically consumes 1.35 w, which is ideal for battery - powered applications. the ad7687 provides the user with an on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7687 is specif ied for use from 2. 3 v to 5.5 v and can be interfaced to any of the 1.8 v to 5 v digital logic family. it is housed in a 10- lead msop or in a tiny 10 - lead lfcsp that saves space and allows flexible configurations. it is pin - for - pin - compatible with the ad7685 , ad7686 , and ad7688 . converter oper ation the ad7687 is a successive approximation adc based on a charge redistribution dac. figure 24 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays function as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition p hase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? open first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the different ial voltage between the inputs in+ and in? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator i nput varies by binary weighted voltage steps (v ref /2, v ref /4 v ref /65536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the device re turns to t he acquisition phase and the control logic generates the adc output code and a busy signal indicator. because the ad7687 has an on - board conversion clock, the serial clock, sck, is not required fo r the conversion process.
data sheet ad7687 rev. e | page 15 of 26 transfer functions figure 25 and table 9 show t he ideal transfer characteristic for the ad7687 . 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb + fsr ? 1 lsb ? fsr + 1 lsb ? fsr ? fsr + 0.5 lsb 02972-025 figure 25 . adc ideal transfer function table 9 . output codes and ideal input voltages description analog input v ref = 5 v digital outp ut code hexa decimal fsr ? 1 lsb +4.999847 v 7fff 1 midscale + 1 lsb +152.6 v 0001 midscale 0 v 0000 midscale ? 1 lsb ?152.6 v ffff ? fsr + 1 lsb ?4.999847 v 8001 ? fsr ?5 v 8000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below ?v ref + v gnd ). typical connection d iagram figure 26 shows an example of the recommended connection diagram for the ad7687 when multiple supplies are available. ad7687 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire inter f ace 5 100nf 100nf 5v 10f 2 7v 7v ?2v 1.8v t o vdd ref 1 0 t o vref 33? 2.7nf 3 4 7v ?2v vref t o 0 33? 2.7nf 3 4 02972-026 1 see vo lt age input reference section for reference selection. 2 c ref is usual l y a 10f ceramic ca p aci t or (x5r). 3 see driver amplifier choice section. 4 optiona l fi l ter. see analog input section. 5 see digi t al inter f ace for most convenient inter f ace mode. figure 26 . typical connection diagram with multiple supplies
ad7687 data sheet rev. e | page 16 of 26 analog input figure 27 shows an equivalent circuit of the input structure of the ad7687 . the two diodes, d1 and d2, provide esd protection for the analog i nputs in+ and in?. take care to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v because this causes these diodes to begin to forward - bias and start conducting current. these diodes can handle a forward - biased current o f 130 ma maximum . t hese over voltage conditions can occur if the supplies of t he input buffer (u1) differ from vdd. in such a case, use an input buffer with a short - circuit current limitation to protect the device . c in r in d1 d2 c pin in+ or in? gnd vdd 02972-027 figure 27 . equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in ?. this differential input scheme allows for rejection of common - mode signals. figure 2 8 shows the typical cmrr over frequency. frequency (khz) cmrr (db) 90 80 70 60 40 50 1 10 100 1000 02972-028 vdd = 5v vdd = 2.5v figure 28 . analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in + or in?) can be modeled as a parallel combination of c apacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 3 k? and is a lumped component made up of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impe dance is limited to c pin . r in and c in make a 1 - pole, low - pass filter that reduces undesirable aliasing effects and limits the noise. if the source impedance of the driving circuit is sufficiently low, the ad7687 can be driven directly. large source impedances significantly affect the ac performance, especially the total harm onic distortion (thd). the maximum source impedance depends on the amount of thd that can be tolerated by the ad7687 . the thd degrades as a function of the source impedance and the maximum input frequency, as shown in figure 29. frequency (khz) thd (db) ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 0 25 50 75 100 02972-029 r s = 250 ? r s = 100 ? r s = 50 ? r s = 33 ? figure 29 . thd vs. analog input frequency and source resistance
data sheet ad7687 rev. e | page 17 of 26 driver amplifier cho ice althou gh the ad7687 is easy to drive, consider the following when selecting a driver amplifier . the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7687 . t he ad7687 has a noise much lower than most of the other 16 - bit adcs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. th e noise coming from the driver is filtered by the ad7687 analog input circuit 1 - pole, low - pass filter made by r in and c in or by an external filter. because the typical noise of the ad7687 is 53 v rms, the snr degradation due to the amplifier is ( ) ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 3db 2 2 2 53 53 20log n loss ne f snr where: f C 3db is either the input bandwidth in mhz of the ad7687 (2 mhz) or the cutoff frequency of an external filter, if one is used. n is the noise gain of the amplifier (for example, +1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. for ac applications, ensure that the thd performance of the driver is commensurate with the ad7687 and that the driver exceeds the thd vs. frequency shown in figure 16. for multichannel multiplexed applications, the driver amplifier and the ad7687 analog input circuit must settle a full - scale step onto the capacitor array at a 16 - bit level (0.00 15%, 15 ppm). s ettling at 0.1% to 0.01% is more commonly specified in the amplifier data sheet . this can differ significantly from the settling time at a 16 - bit level and must be verified prior to driver selection. table 10 . recommended driver amplifiers. amplifier typical application ad8021 very low noise and high frequency ad8022 low noise and high frequency ad8031 high frequency and low power ad8519 small, low power and low frequency ad8605 , ad8615 5 v single - supply, low power ad8655 5 v single - supply, low noise ada4841 -2 very low noise, small, and low power ada4941 -1 very low noise, low power single - ended -to - differential op184 low power, low noise, and low frequency single - to- differential driver f or applications using a single - ended analog signal, either bipolar or unipolar, a single - ended - to - differential driver (like the one shown in figure 30) allows for a differential input into the part . when provided a single - ended input signal, this configura tion produces a differential v ref with midscale at v ref /2. u2 n ad7687 in+ in ref u1 analog input (10v, 5v, ..) 10f 100nf n vref vref n n 100nf vref 02972-030 figure 30 . single - ended - to - differential driver circuit voltage reference in put the ad7687 voltage reference input, ref, h as a dynamic input impedan ce and must therefore be driven by a low impedance source with su fficient decoupli ng between the ref and gnd pins ( as explained in the layout section ) . for optimum performance, drive the ref pin with a low output impedance amplifier (such as the ad8031 or the ad8605) a s a reference buffer with a 10 f (x5r, 0805 size) ceramic chip decoupling capacitor . if an unbuffered reference voltage is used, the decoupling value depends on the ref erence used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr431 , adr433 , adr434 , or adr435 reference. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is n o need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7687 is sp ecified for use over a wide operating range of 2.3 v to 5.5 v. unlike other low voltage converters, it has a low enough noise to design a 16 - bit re solution system with low voltage suppl ies while maintaining respectable performance. it uses two power supply pins: a core supply , vdd , and a digital input/outpu t interface supply , vio. vio allows direct interface with any logic between 1.8 v and vdd. vio and vdd can be powered by the same source, reducing the number of supplies required in the overall design . the ad7687 is independent of power supply sequencing betwe en vio and vdd.
ad7687 data sheet rev. e | page 18 of 26 additionally, it is resistant to power supply variations over a wide frequency range. figure 31 shows the power supply rejection ration (psrr) of the device over frequency. frequency (khz) psrr (db) 100 95 90 85 80 75 70 65 60 55 50 1 10 100 1000 10000 02972-031 vdd = 5v vdd = 2.5v figure 31. psrr vs. frequency the ad7687 powers down automatically at the end of each conversion phase, and consequentially its power consumption scales linearly with the sampling rate, as shown in figure 32. this makes the device ideal for low sampling rate (even a few sps) and low battery-powered applications. sampling rate (sps) operating current ( ? a) 1000 10 0.1 0.001 10 100 1000 10000 100000 1000000 02972-032 vio vdd = 5v vdd = 2.5v figure 32. operating cu rrents vs. sampling rate supplying the adc from the reference with its low operating current, the ad7687 can be supplied directly by the reference circuitry (see figure 33). the reference line is driven by one of the following: ? the system power supply directly. ? a reference voltage with enough current output capability, such as the adr435. ? a reference buffer, such as the ad8031 , which can also filter the system power supply (see figure 33). ad8031 ad7687 vio ref vdd 10 ? f 1 ? f 10 ? 10k ? 5v 5v 5v 1 ? f 1 02972-033 1 optional reference buffer and filter. figure 33. example of application circuit digital interface though the ad7687 has a reduced number of pins, it offers flexibility in its serial interface modes. when in cs mode, the ad7687 is compatible with spi, qspi, digital hosts, and dsps, such as the blackfin? processors or the high performance, mixed-signal dsp family. in this mode, the ad7687 uses either a 3-wire or a 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections and is useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. when in chain mode, the ad7687 provides a daisy chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the device operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high, and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is always selected. the initial state of sdo on power up is indeterminate. therefore, to put sdo in a known state, initiate a conversion and clock out all data bits. in either mode, the ad7687 offers the option of forcing a start bit in front of the data bits. use this start bit as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled ? in the cs mode if cnv or sdi is low when the adc conversion ends (see figure 37 and figure 41). ? in the chain mode if sck is high during the cnv rising edge (see figure 45).
data sheet ad7687 rev. e | page 19 of 26 cs m o de , 3 - wire w ithout busy indicator this mode is usually used when a single ad7687 is connected t o an spi - compatible digital host. figure 34 shows t he connection diagram and figure 35 gives the corresponding timing. with sdi tied to vio, a rising edge on cnv initiates a conversion , selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continue s to completion irrespective of the state of cnv. for instance, it can be us eful to bring cnv low to select other spi devices, such as analog multiplexers, but cnv must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicato r (see t conv in table 5 ) . when the conversion is complete , the ad7687 enters the acquisition phase and powers down. whe n cnv goes low, the msb is output onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the dat a, a digital host using the sck falling edge allows a fas ter reading rate (provided it has an acceptable hold time) . after the 16th sck falling edge , or when cnv goes high, whichever is earlier, sdo returns to hig h impedance. cnv sck sdo sdi data in clk convert vio digital host ad7687 02972-034 figure 34 . cs mo de , 3 - wire without busy indicator connection diagram (sdi high) sdo d15 d14 d13 d1 d0 t dis sck 1 2 3 14 15 16 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 02972-035 figure 35 . cs mod e , 3 - wire without b usy indicator serial interface timing (sdi high)
ad7687 data sheet rev. e | page 20 of 26 cs m ode , 3 - wire with busy indic ator this mode is usually used when a single ad7687 is connected to an spi - compatible digital host having an interrupt input. figure 36 shows t he connection diagram and figure 37 gives the corresponding timin g. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the con version irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexer s, but cnv must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator (see t conv in table 5 ). when the conversion is complete, sdo goes from high to low impedance. with a pull - up on the sdo lin e, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. when using this option, select the value of the pull - up resistor such that it maintains an appropriat e rise tim e on th e sdo line for the application. this is a function of the resistance of the pull - up and the capacitance of the sdo line. the ad7687 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falli ng edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edg e allows a faster reading rate (provided it has an acceptable hold time) . after the optional 17th sck falling edge, or when cnv goes high, whichever is earlier, sdo returns to high impedance. if multiple ad7687 devices are selected at the same time, the sdo output pin handles this contention without damage or induced latch - up. k eep this contention as short as possible to limit extra power dissipation. data in irq clk convert vio digital host 02972-036 47k ? cnv sck sdo sdi vio ad7687 figure 36 . cs mo de , 3 - wire with busy indicator connection diag ram (sdi high) sdo d15 d14 d1 d0 t dis sck 1 2 3 15 16 17 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc t cnvh t acq acquisition sdi = 1 02972-037 figure 37 . cs mode , 3 - wire with busy indicator serial interface timing (sdi high)
data sheet ad7687 rev. e | page 21 of 26 cs mo de , 4 - wire w ithout busy indicator this mode is usually used when multiple ad7687 devices are connected to an spi - compatible digital host. figure 38 shows a connection diagram example using two ad7687 devices and figure 39 gives the corresponding timing . with sdi high, a rising edge on cnv initiates a conversion, selects the cs m ode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7687 enters the acquisition phase and powers down. each adc result can be read by bringing low its sdi input, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate (provided it has an acceptable hold time) . af ter th e 16th sck falling edge, or when sdi goes high, whichever is earlier, sdo returns to high impedance and another ad7687 can be read. data in clk cs1 convert cs2 digital host 02972-038 cnv sck sdo sdi ad7687 cnv sck sdo sdi ad7687 figure 38 . cs mode , 4 - wire without bus y indicator connection diagram sdo d15 d14 d13 d1 d0 t dis sck 1 2 3 30 31 32 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 14 15 t sck t sckl t sckh d0 d15 d14 17 18 16 sdi(cs2) 02972-039 figure 39 . cs mod e , 4 - wire without busy in dicator serial interface timing
ad7687 data sheet rev. e | page 22 of 26 cs mode, 4-wire with busy indicator this mode is usually used when a single ad7687 is connected to an spi-compatible digital host, which has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. figure 40 shows the connection diagram and figure 41 gives the corresponding timing. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can select other spi devices, such as analog multiplexers, but sdi must be returned low before th e minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high to low impedance. with a pull-up on the sdo line, this transition can act as an interrupt signal to initiate the data readback controlled by the digital host. when using this option, select the value of the pull-up resistor such that it maintains an appropriate rise time on the sdo line for the application. this is a function of the resistance of the pull-up and the capacitance of the sdo line. the ad7687 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate (provided it has an acceptable hold time). after the optional 17th sck falling edge, or sdi going high, whichever is earlier, the sdo returns to high impedance. data in irq clk convert cs1 vio digital host 02972-040 47k ? cnv sck sdo sdi ad7687 figure 40. cs mode, 4-wire with busy indicator connection diagram sdo d15 d14 d1 d0 t dis sck 1 2 3 15 16 17 t sck t sckl t sckh t hsdo t dsdo t en conversion a cquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 02972-041 figure 41. cs mode, 4-wire with busy indicator serial interface timing
data sheet ad7687 rev. e | page 23 of 26 chain mod e w ithout busy indicator use this mode to daisy - chain multiple ad7687 devices o n a 3 - wire serial interface. this feature is useful for reducing component count and wiring connections, for isolated multiconverter applications , or for systems with a limited interfacing capacity (for example) . data readback is analogous to clocking a shift register. figure 42 shows a connection diagram example using two ad7687 devices and figure 43 gives the corresponding timing. when sdi and cnv are low, sdo is driven low. with sdi and sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this m ode, cnv is held high during the conversion phase and the subsequen t data readback. when the conversion is complete, the msb is output onto sdo and the ad7687 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are then shifted out by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register ; these data bits are also shifted in by the sck falling ed ge. each of the n adcs in the chain outputs it s data msb first. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using t he sck falling edge allows a faster reading rate and, consequently , more ad7687 devices in the chain ( provided the digital host has an acceptable hold time ) . after the 16 n th sck falling edge or cnv rising edge, whichever is earlier, sdo is driven low again. the maximum conversio n rate can be reduced due to the total readback time. for example , using a digital host with a 3 ns set - up time and 3 v interface, up to eight ad7687 devices daisy - chained on a 3 - wire port can be run at a maximum effective conv ersion rate of 220 ksps. clk convert data in digital host 02972-042 cnv sck sdo sdi ad7687 b cnv sck sdo sdi ad7687 a figure 42 . chai n mode without busy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 30 31 32 t ssdisck t hsdisc t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 14 15 t sck t sckl t sckh d a 0 17 18 16 sdi a = 0 sdo b d b 15 d b 14 d b 13 d a 1 d b 1 d b 0 d a 15 d a 14 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 02972-043 figure 43 . chain mode without busy indicator serial inter face timing
ad7687 data sheet rev. e | page 24 of 26 c hain mode with busy indicator this mode can also be used to daisy - chain multiple ad7687 devices on a 3 - wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for isolated multiconverter applications or for systems with a limited interfacing capacity (for example) . data read back is analogous to clocking a shift register. figure 44 shows a connection diagram example using three ad7687 devices, and figure 45 gives the corresponding timing . when sdi and cnv are low, sdo is driven low. with sdi low and sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the bus y indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7687 c in figure 44 ) is driven high . this transition on sdo can act as a busy indicator to trigger the data readback controlled by the digital host. the ad7687 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are then clocked out, ms b first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register ; these data bits are also shifted in by the sck falling edge . each of the n adc s in the c hain outputs its data msb first. the data is valid on both s ck edges. a lthough the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more ad7687 devices in the chain (provided the di gital host has an acceptable hold time). after the optional (16 n) + 1 th sc k falling edge or cnv rising edge, whichever is earlier, sdo is driven low again. the maximum conversion rat e may be r educed due to the total readback time. for example, using a digital host with a 3 ns set - up time and 3 v interface, up to eight ad7687 devices daisy - chained on a 3 - wire port can be run at a maximum effective conversion rate of 220 ksps . clk convert data in irq digital host 02972-044 cnv sck sdo sdi ad7687 c cnv sck sdo sdi ad7687 a cnv sck sdo sdi ad7687 b figure 44 . chain mode with busy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 35 47 48 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 4 15 t sck t sckh t sckl d a 0 17 34 16 sdo b = sdi c d b 15 d b 14 d b 13 d a 1 d b 1 d b 0 d a 15 d a 14 49 t ssdisck t hsdisc t hsdo t dsdo sdo c d c 15 d c 14 d c 13 d a 1 d a 0 d c 1 d c 0 d a 14 19 31 32 18 33 d b 1 d b 0 d a 15 d b 15 d b 14 t dsdosdi t ssckcnv t hsckcnv 02972-045 d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi figure 45 . chain mode with busy indicator serial interface timing
data sheet ad7687 rev. e | page 25 of 26 application s information layout providing a steady and stable reference voltage to the ad7687 is critical for device operation. prioritize d esign tasks aimed at preventing vo ltage fluc tuations at this node . decouple t he ref pin , which has a dynamic input impedance, with minimal parasitic induct ances (see the converter operation se ction ) . achieve thi s by placing the reference decoupling c eramic capacitor as close as physically possible the ref and gnd pins and connecting it with wide, low impedance traces. l imiting sources of noise on the analog signal nodes is imperative in high precision adc systems . the digital lines controlling the ad7687 have the potential to radiate noise that can couple into the analog signals; therefore, ensure that these two types of signals are separated and c onfined to different areas of boards housing the ad7687 . ne ver allow f ast switching signals (such as cnv or clocks) to run near analog signal paths, and avoid physical c rossover of digital and ana log signals . do not route d igital lines under the ad7687 without a ground plane providing adequate isolation between the two . t o facilitate these design tasks, the analog and digital pins are located on separate sides of the device (see figure 46 ) . printed c ircuit boards (pcbs) ho using the ad7687 must cont ain at least one ground plane. connecting analog and digital ground on the board is not required; however, connecting these planes underneath the ad7687 is recommended. finally , decouple the power supply pins of the ad7687 (vdd and vio) with ceramic capacitors (typically 100 nf) pla ced close to the ad7687 and connected using short and wide traces to provide lo w impedance paths and reduce the effect of glitches on the power supply lines. figure 46 and figure 47 show a n example of a layout following these rules . 02972-046 figure 46 . example of layout of the ad7687 (top layer) 02972-047 figure 47 . example of layout of the ad7687 (bottom layer) evaluating the perfo rmance of the ad7687 t he e va l - ad7687sdz evaluation board documentation outlines o ther recommended layouts for the ad7687 . the evaluation board package include s a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the e va l - sdp - cb1z .
ad7687 data sheet rev. e | page 26 of 26 outline dimensions com pli ant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 copla narit y 0.10 0.2 3 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 iden ti fie r 15 max 0.95 0.85 0.75 0.15 0.05 figure 48 . 10- lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a se a ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t o p view bottom view 0.20 min figure 49 . 10 - lead lead frame chip scale package [lfcsp_wd ] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters ordering guide model 1 , 2 , 3 integral nonlinearity temperature range package description pac kage option ordering quantity branding ad7687brmz 1.5 lsb ?40c to +85c 10- lead msop, tube rm -10 50 c3q AD7687BRMZRL7 1.5 lsb ?40c to +85c 10 - lead msop, reel rm - 10 1,000 c3q ad7687bcpz -r2 1.5 lsb ?40c to +85c 10- lead lfcsp_wd, reel cp -10-9 250 c3q ad7687bcpzrl7 1.5 lsb ?40c to +85c 10- lead lfcsp_wd, reel cp -10-9 1,500 #c03 eval - ad7687sdz evaluation board eval - sdp - cb1z controller board 1 z = rohs compliant part, # denotes rohs compliant product, ma y be top or bottom marked. 2 the eval - ad7687sdz can be used as a standalone evaluation board or in conjunction with the eval - sdp - cb1z for evaluation and/or demonstration purposes. 3 the eval - sdp - cb1z allows a pc to control and communicate with all analog devices, inc. evaluation boards ending in the sdz desi gnator. ? 2005 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02972 - 0 - 12/15(e)

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